(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing the pattern sensitivity of an ozone-TEOS dielectric layer in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, a conducting layer is deposited over a semiconductor substrate containing semiconductor device structures such as gate electrodes and source and drain regions. The conducting layer is patterned to form conducting lines. A dielectric layer is deposited over the conducting lines and within the gaps between conducting lines. Typically, the dielectric layer is composed of ozone-TEOS (tetraethoxysilane).
Pattern sensitivity has been found to be a severe problem in ozone-TEOS deposition. The phenomenon has been that ozone-TEOS deposits slower in areas overlying dense metals. This can lead to problems such as voids within the dielectric layer. We have found that the degree of pattern sensitivity depends strongly on deposition temperature. However, the quality of the ozone-TEOS layer degrades at reduced temperatures. It is desired to find a method of forming a high quality ozone-TEOS layer with reduced pattern sensitivity.
U.S. Pat. No. 5,271,972 to Kwok et al teaches the deposition of an ozone-TEOS layer with power ramp down during the last few seconds. U.S. Pat. No. 5,356,722 to Nguyen et al teaches the use of a plasma enhanced seed oxide consisting of a plasma, TEOS, and a nitrogen-containing gas. Co-pending U.S. patent application Ser. No. 08/494,630 to the same inventors teaches a method of reducing pattern sensitivity by using an underlayer of PE-SiH.sub.4 or PE-SiN.